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Date:26-Apr-2010
Title:Doctoral position available @ ONERA (The French Aerospace Lab) Centre Midi Pyrénnées
Hits:638
Contributed by: Rémi Delmas
Keywords:BMC, Verification, null, null, null, null, null, null
 
  
 

This thesis is proposed by ONERA's information processing and systems modelling department in Toulouse, France, in partneship with Rockwell Collins France (French subsidiary of Rockwell Collins Inc.), a leading designer and provider of critical aerospace systems, enjoying a internationally renowned expertise in formal methods.

Critical systems and software are subject to diverse and drastic requirements such as functional correctness under hard real-time constraints, fault-tolerance constraints, reconfiguration constraints, etc. Over the years, a range of model driven engineering techniques and formal analysis methods and techniques were developed (scheduling analysis, real-time performance prediction, automatic bug finding, automatic proof of absence of bug, …) and refined to reach a high maturity.

Despite these continuous advances in formal methods, users often experience technical difficulties in scaling up formal methods to models of real world systems, either because of their important size, because or because of their inherent computational complexity (when they make use of non linear integer arithmetic, or floating point arithmetic for instance). Methodological and process issues can also come in the way, but this thesis will be primarily focused on the technical side of the problem.

Nevertheless, it seems some progress can be achieved on these technical issues by establishing a tight cooperation between different and mature approaches to formal verification.

In particular, SMT-based temporal model checking techniques (MC), which allow to verify safety and liveness properties on transition systems, have gained momentum thanks to the recent and dramatic advances in SMT solvers performance, invariant strengthening for k-induction based techniques and Craig interpolant generation techniques for heterogeneous logics. Still, proofs can fail, and extra non-trivial information (i.e. lemmas) often has to be manually added to a model to allow a proof to be obtained.

Similarly, abstract interpretation (AI) techniques have become extremely effective, but are somehow dedicated to the analysis of predefined property patterns on imperative code, such as out of bounds accesses in arrays, integer overflows/underflows, or to finding bounds on the error between an ideal computation using real numbers and its implementation using floating point numbers.

The Ph.D. student will have to study in which way these two families of techniques (MC/AI) can complement each other so as to overcome their own limitations, hopefully extending the range of critical aerospace systems that can be addressed with formal methods.

Full details and contact information available in this ONERA PDF document

The thesis will follow a CIFRE convention (Click for CIFRE financing information)
 
 
 

 
  
Date:17-Dec-2009
Title:Tarmo: A Framework for Parallelized Bounded Model Checking
Hits:730
Contributed by: Siert Wieringa
Keywords:BMC, Verification, null, null, null
 
  
 
The following paper and the software described in it is now available online: Siert Wieringa, Matti Niemenmaa and Keijo Heljanko, Tarmo: A Framework for Parallelized Bounded Model Checking, In Lubos Brim and Jaco van de Pol, editors, Proceedings of the 8th International Workshop on Parallel and Distributed Methods in verifiCation (PDMC09), volume 14 of Electronic Proceedings in Theoretical Computer Science (EPTCS), pages 62-76, 2009. Our Tarmo framework is an approach to parallelizing BMC by parallel SAT solving of the sequence of incrementally encoded SAT instances that follow from a single BMC task. The satisfiability of an instance in such a sequence corresponds to the existence of a counterexample of a specific length. The available Tarmo software implements our generic shared clause database architecture which allows sharing clauses between SAT solver processes that are working on possibly different instances from one such sequence.
 
 
 

 
  
Date:01-Mar-2009
Title:Book "Satisfiability & Verification" published
Hits:1191
Contributed by: Marc Herbstritt
Keywords:BMC, DPLL, Verification, QBF, EDA, branching heuristics, phase transition, Linear Programming, variable ordering heuristic, symmetry, null, null, null, null
 
  
 
Dear all,

recently, my book entitled "Satisfiability & Verification: From Core Algorithms to Novel Application Domains" was published. It is available from your preferred Amazon-dealer:

[amazon.com]
[amazon.co.uk]
[amazon.de]

Please support satisfiability-related research by recommending this book to your library.

About the content:
Verification techniques that rely on solving instances of the satisfiability problem (SAT) have become a major approach within the last decade to ensure the correctness of systems.
This book is a revised version of my dissertation that handles issues ranging from core aspects of SAT-solvers to novel application domains of SAT-based verification.
The first part of the book serves as a brief but concise introduction to SAT-based verification techniques by describing basic data structures (e.g. And/Inverter-graphs) and algorithms (zChaff) as well as traditional verification scenarios (e.g. combinational equivalence checking and bounded model checking). Many examples simplify the understanding of the described techniques. These chapters may also serve as a graduate text for an introduction to the topic.
The second part of the book presents the results of my research, e.g. C/V-ratio based variable selection, parametric data structures for SAT-based bounded model checking, bounded model checking of linear hybrid automata, and finally - which constitutes the biggest part - bounded model checking of partial circuit designs. The book comes with detailed references and a helpful index.

Table of contents:
1 Introduction.- 1.1 Contribution.- 1.2 Book Structure.- 2 Preliminaries.- 2.2 Boolean Functions.- 2.3 Representation of Boolean Functions.- 2.4 Propositional Logic and Satisfiability.- 2.5 Quantifier-free Extension of Propositional Logic: 01X-Logic.- 2.6 Quantified Boolean Formulas.- 3 Verification Models and Techniques.- 3.1 Combinational Equivalence Checking.- 3.2 Bounded Model Checking.- 3.3 Linear Hybrid Automata.- 3.4 Blackbox Designs.- 4 Extensions and Applications of SAT-Engines.- 4.1 Branching Heuristics.- 4.2 Conflict Analysis, Clause Reuse, and Parametric Data Structures.- 5 Bounded Model Checking of Blackbox Designs.- 5.1 BMC of Blackbox Designs via 01X-Logic.- 5.2 BMC of Blackbox Designs via Quantified Boolean Formulas.- 5.3 Combining 01X-Logic and QBF.- 5.4 Formalization and Proof of Correctness.- 5.5 Lifting in the Context of Automated Blackbox Synthesis.- 5.6 Relational versus Functional Transition Representation.- 5.7 Combining SAT-based BMC and BDD-based SMC.- 5.8 Summary.- 6 Conclusions.- Acknowledgements.- References.- Index.

Thank you for your interest and support.

Marc Herbstritt

 
 
 

 

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